JK Flip flop | Computer Organization And Architecture Tutorials

The JK Flip flop can be viewed as a modification of the SR Flip flop. The intermediate state in a JK Flip flop is more refined and precise than that of an SR Flip flop.

Design of JK Flip flop

The design of a JK Flip flop is similar to that of an SR Flipflop. The $Q$ output is connected back to the input of NAND gate $G_2$ and $\overline Q$ output is connected back to the input of NAND gate $G_1$ .

jk flip flop circuit diagram — **JK Flip flop circuit diagram**

Working of JK Flip flop

When $J$ is 1 and $K$ is 0, the $Q$ output goes 1 on the triggering edge of the clock pulse, and the flip-flop is SET. When $J$ is 0 and $K$ is 1, the $Q$ output goes 0 on the triggering edge of the clock pulse, and the flip-flop is RESET.

When both $J$ and $K$ are 0, the output does not change from its prior state. When $J$ and $K$ are both 1, the output of the JK flip-flop will toggle between 1 and 0. This is called the race-around condition in a JK Flipflop. This is described in the following truth table.

$Clk$	$J$	$K$	$Q_{n+1}$
0	X	X	$Q_n$
1	0	0	$Q_n$
1	0	1	0
1	1	0	1
1	1	1	$\overline Q_n$ (Toggle)

Truth table

$Q_n$	$J$	$K$	$Q_{n+1}$
0	0	0	0
0	0	1	0
0	1	0	1
0	1	1	1
1	0	0	1
1	0	1	0
1	1	0	1
1	1	1	0

Characteristic table

$Q_n$	$Q_{n+1}$	$J$	$K$
0	0	0	X
0	1	1	X
1	0	X	1
1	1	X	0

Exctitation table

Expressions for $J$ , $K$ and $Q_{n+1}$ can be obtained from the table using the K-Map technique as follows.