A Binary Coded Decimal or a Decade counter is a counter that can count 10 states. A 4 bit binary counter will act as a decade counter by skipping six outputs out of the 16 outputs.
The following truth table describes the counting operation of a decade counter.
| Clock |  |
 |
 |
 |
|---|---|---|---|---|
| 0 | 0 | 0 | 0 | 0 |
| ↑ | 0 | 0 | 0 | 1 |
| ↑ | 0 | 0 | 1 | 0 |
| ↑ | 0 | 0 | 1 | 1 |
| ↑ | 0 | 1 | 0 | 0 |
| ↑ | 0 | 1 | 0 | 1 |
| ↑ | 0 | 1 | 1 | 0 |
| ↑ | 0 | 1 | 1 | 1 |
| ↑ | 1 | 0 | 0 | 0 |
| ↑ | 1 | 0 | 0 | 1 |
| ↑ | 1 | 0 | 1 | 0 |
State Diagram of Decade Counter
A counter is described by a state diagram, which shows the sequence of states through which the counter goes through when it is clocked.
The count starts from 0000 (zero) to 1001 (9) and then on encountering 1010 (10) it resets to 0000.
Decade Counter Circuit Diagram
The diagram given below shows an asynchronous decade counter constructed using JK flip flops.
J and K inputs of all flip flops are set to logic 1. Two asynchronous inputs PRESET(PRE) and CLEAR(CLR) is given to all the flip flops. They have control over the outputs (
and 
) regardless of clock input status. Both are active-low inputs.
When the PRESET input is activated, the flip-flop will be set regardless of any of the inputs or the clock. When the clear input is activated, the flip-flop will be reset, regardless of any of the inputs or the clock. PRESET is maintained at logic 1, hence it will not be activated.
When the clock pulse advances the counter to count 10 (1010), outputs of flip flops B and C will be high. As we know that for high inputs, the NAND gate output will be low. The NAND gate output is connected to clear input, so it resets all the flip flop stages in the decade counter. This means the counter will restart after count 9.
