SR flip flop

Flip flops are synchronous bistable devices, also known as bistable multivibrators. The term synchronous means that changes in the output occur in synchronization with control input called a clock.

SR Flip flop diagram
SR Flip flop block diagram

Circuit Diagram of SR Flip flop

The SR flip flop is designed by adding two NAND gates to a basic SR latch. The advantage of this clocked circuit is that the inputs R and S are considered only when the clock pulse is high. The circuit of the SR flip flop using the NAND gate is shown below.

SR Flip flop using NAND gate
SR Flip flop circuit diagram

Working of SR Flip flop

When Clk = 0, irrespective of the value of S or R, the value of Q and \overline Q will be whatever the values stored in the previous state of the flip flop.

When Clk = 1, the output of the first two NAND gates, followed by inputs S and R, will be \overline S and \overline R. When S=1, we get SET state and when R=1, we get the RESET state.

As before, the condition R = S = 1 is indeterminate and should be avoided when Clk is also 1.

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This operation is described in the following truth table. Here Q_n indicated the present state and Q_{n+1} indicates the next state. The characteristics table can be obtained from the truth table is given below.

Clk S R Q_{n+1}
0 X X Qn
1 0 0 Qn
1 0 1 0
1 1 0 1
1 1 1 Invalid

Truth table

Q_n S R Q_{n+1}
0 0 0 0
0 0 1 0
0 1 0 1
0 1 1 X
1 0 0 1
1 0 1 0
1 1 0 1
1 1 1 X

Characteristics table

From these two tables, we know the transition from the present state to the next state. To find the latch input conditions that will cause the specified transition, We need a table that lists the required inputs for a given change of state. It is called an excitation table.

We can also obtain the expression for Q_{n+1} from the characteristics table using the K-Map technique as follows.

Q_n Q_{n+1} S R
0 0 0 X
0 1 1 0
1 0 0 1
1 1 X 0

Excitation Table

SR Flip flop K Map

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