Shift Registers

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Registers

A register is a collection of flip-flops, each of which can store one bit of information. An n-bit register is a group of n flip-flops that can store binary information of n bits. Register memory is the smallest and most powerful type of memory in a computer. It stores frequently used data, instructions, and memory addresses for use by the CPU.

in most digital systems, a master clock generator provides a continuous train of clock pulses. The clock pulse is applied to all of the flip-flops and registers in the system.

The information stored in registers can be transferred using shift registers. The registers that shift the bits to the left are referred to as a shift left registers and the registers that shift the bits to the right are referred to as shift right registers.

The shift register uses D flip flops. It is because the D flipflop can operate moving data from the input to the output while a clock pulse is applied.

In shift registers, data can be entered and extracted sequentially or parallelly. Based on this, Shift registers are classified as follows:

SISO – Serial In Serial Out
SIPO – Serial In Parallel Out
PISO – Parallel In Serial Out
PIPO – Parallel In Parallel Out

SISO (Serial In Serial Out) Shift Registers

The SISO is on the simplest of all the shift registers. The block diagram of a 4-bit shift right SISO shift register is shown below. Each flipflop has one input(D_i), one output and (Q_i) and a clock pulse input.

In SISO shift registers, the input and output operation is performed serially. The data is loaded into the input of the left-most flip-flop bit by bit. The data bit is shifted from one flip-flop to the next for each clock pulse. The data inserted will be received bit by bit for each clock pulse on the output side of the rightmost flipflop. An n-bit SISO shift register requires 2n-1 clock pulses to shift n bit data.

Initially, the output of all the flip-flops is assumed to be logic 0.
Assume the data at the $D_{in}$ input terminal is 1.
The logic 1 at the input $D_{in}$ is shifted to the output of the first flip-flop $Q_3$ during the first clock pulse. Similarly, the data input to the remaining flip-flops is shifted by one position.
The logic 1 at the first and second flip-flop inputs is shifted by one position during the second clock pulse. The logic 0 input at the input of the remaining flip-flops is also shifted by one position.
This shifting process is repeated for each clock pulse. The loaded data bit ‘1′ will be received at the output terminal $Q_0$ at the end of the fourth clock pulse.
It takes 7 clock pulses to output all bits.

The truth table of shifting data 1111 is given below.

$Clk$	$Q_3$	$Q_2$	$Q_1$	$Q_0$
Initially	0	0	0	0
↓	1	0	0	0
↓	1	1	0	0
↓	1	1	1	0
↓	1	1	1	1

This operation can be also represented using a timing diagram as follows.

siso timing — Shift Right Registers Timing Diagram

SIPO (Serial In Parallel Out) Shift Registers

In a SIPO shift register, the data is loaded serially bit by bit. After shifting data inputs, the output of each flip-flop can be taken out in parallel. The block diagram of a 4-bit shift right SIPO shift register is shown below.

The data shifts from one stage to the next for each negative edge triggering of the clock signal. We can access the outputs of all D flip-flops at the same time. So we get parallel outputs from the shift register at the same time.

In SISO shift registers, the input and output operation is performed serially. The data is loaded into the input of the left-most flip-flop bit by bit. The data bit is shifted from one flip-flop to the next for each clock pulse. The data loaded will be received bit by bit for each clock pulse on the output side of the rightmost flipflop.

An n-bit SIPO shift register requires n clock pulses to shift n bit data. That is, the above 4-bit shift register only requires 4 clock pulses to shift the data given in the input.

PIPO (Parallel In Parallel Out) Shift Registers

In a PIPO shift register, the input data is loaded parallel into each flip-flop and the output is received from each flip-flop parallelly.

piso 2 2 — Parallel In Serial Out Shift Register

It is used for temporary data storage or as a time delay device. Only a single clock pulse is required to load and unload data in a PIPO shift register.

PISO (Parallel In Serial Out) Shift Registers

In a PISO shift register data is loaded into each flip flop in parallel, and the inserted data is received at the output serially.

piso 2 1 — Parallel In Parallel Out Shift Register

The $SHIFT/ \overline{LOAD}$ control signal decides the shifting and parallel loading actions. Applying 0 to the control signal, will disable the AND gates 1, 3, 5 and enable the AND gates 2, 4, 6. It will make the parallel data at the inputs(B0, B1, B2, B3) get stored in the respective flip-flops. So parallel loading happens when the control signal is set to 0, that is when $\overline{LOAD}$ is active. Only a single clock pulse is required for this loading operation.

When the control signal is 1, it will enable the AND gates 1, 3, 5 and disable the gates 2, 4, 6. On applying a clock pulse, the data at the input of each flip-flop is shifted to its output. The data is shifted serially upon the application of each clock pulse. The serial output is obtained from the output(Q₀) of the last flip-flop.

An n-bit PiSO shift register requires n-1 clock pulses to shift n bit data.

Applications of Shift Registers

Shift registers are used to store temporary data.
Shift registers are also used as counters (Ring counter and Johnson Ring counter).
Shift registers can be used for data transfer and manipulation.
A PISO shift registers can be used to convert parallel data into serial data.
A SIPO shift registers can be used to convert serial data into parallel data.
A SISO and PISO registers can be used to add time delay to digital circuits.