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Synchronous Counters

The clock inputs of all the individual flip-flops are clocked together at the same time by the same clock signal, giving rise to the name “synchronous counter.” Because all of the flip-flops are clocked together simultaneously (in parallel) at the same time, changes in output occur in “synchronisation” with the clock signal.

As a result, all of the individual output bits change state at the same time, in response to the common clock signal, with no ripple effect and thus no propagation delay, as in asynchronous counters.

How to design a synchronous counter

The designing of synchronous counters follows the steps given below :

  1. Decide the number of flip flops required.
  2. Decide the type of flip flop and draw excitation table of flip flop.
  3. Draw the state diagram and circuit excitation table.
  4. Obtain simplified equations for inputs using K-Map.
  5. Draw the logic diagram based on the equations obtained.

Designing a 2-bit Synchronous up Counter

Step 1

Number of flipflops = 2, since it is a 2-bit counter.

Step 2

The flipflop we are going to use is JK flip flop. Excitation table of JK flip flop is:

Q_n Q_{n+1} J K
0 0 0 X
0 1 1 X
1 0 X 1
1 1 X 0
Step 3

Since it is a 2-bit counter, it has 22 = 4 states. It can count from 0 to 3. Hence, the state diagram can be drawn as shown below :

 2-bit Synchronous up Counter

Using the excitation table of the flip-flop, we have to enter the flip-flop inputs, that are capable of producing the next state of the counter from the present state in a table. For this we create Circuit Excitation Table.

Q_1 Q_2 Q*_1 Q*_2 J_1 K_1 J_2 K_2
0 0 0 1 0 X 1 X
0 1 1 0 1 X X 1
1 0 1 1 X 0 1 X
1 1 0 0 X 1 X 1
Step 4
 2-bit Synchronous up Counter
Step 5

Based on the equations we found, we have to design the counter. The diagram hence constructed is shown below. (Note that the clock input is given to all flip flops and here, MSB is at Q1 and LSB is at Q2.)

 2-bit Synchronous up Counter

Designing a 3-bit Synchronous up Counter

Step 1

The number of flip-flops needed is 3 since it’s a 3-bit counter.

Step 2

The flipflop we are going to use is T flip flop. The excitation table of JK flip flop is:

Q_n Q_{n+1} T
0 0 0
0 1 1
1 0 1
1 1 0
Step 3

Since it is a 3-bit counter, it has 23 = 8 states. It can count from 0 to 7. Hence, the state diagram can be drawn as shown below :

image 3

Using the excitation table of the flip-flop, we have to enter the flip-flop inputs, that are capable of producing the next state of the counter from the present state in a table. For this, we create Circuit Excitation Table.

Q_1 Q_2 Q_3 Q_1* Q_2* Q_3* T_C T_B T_A
0 0 0 0 0 1 0 0 1
0 0 1 0 1 0 0 1 1
0 1 0 0 1 1 0 0 1
0 1 1 1 0 0 1 1 1
1 0 0 1 0 1 0 0 1
1 0 1 1 1 0 0 1 1
1 1 0 1 1 1 0 0 1
1 1 1 0 0 0 1 1 1
Step 4
image 4
Step 5

Based on the equations we found, we have to design the counter. The diagram hence constructed is shown below. Here MSB is at QC and LSB is at QA.

3 bit synchronous up counter

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