Ring Counter
A ring counter is also known as SISO (serial in serial out) shift register counter. The designing of the ring counter can be done by using four D-Flip Flops with a common clock signal and an overriding input that can be connected to preset and clear.
All the flip-flops are arranged in series such that the output of the preceding flip-flop is fed as an input to the immediate next flip-flop. The output of the last flip-flop is given as an input to the first flip-flop.
The ring counter is a Synchronous Counter and also, number of states = number of flip flops used. Therefore, a 4-bit Ring Counter can count 4 states.
The overriding input(ORI) is connected to the PRE input of the first flip flop and the CLR input of all other flip flops. They are active low, and hence, when ORI is low(0), the first flip flop is SET(when PRE=0, Q 0 =0) and all other flip flops are RESET (when CLR=0, output=0).
- Initially, the ORI is low, therefore the state of counter is 1000.
- After this, ORI is made high and hence the flip flops give outputs based on D input on encountering the negative edge of incoming Clock pulses(Clk).
- Ring counters have only one bit high at any instant of time.
The states of counter affected by each clock pulse are given below. The bit patterns repeat after every 4 clock cycles.
| ORI | Clock |  |
 |
 |
 |
|---|---|---|---|---|---|
 |
???? | 1 | 0 | 0 | 0 |
| 1 | ???? | 0 | 1 | 0 | 0 |
| 1 | ???? | 0 | 0 | 1 | 0 |
| 1 | ???? | 0 | 0 | 0 | 1 |
| 1 | ???? | 1 | 0 | 0 | 0 |
Johnson’s Counter
Also known as Inverse Feedback Counter or Twisted Ring Counter. Here, a D-flip flop is used to construct a Johnson Counter. All flip-flops are arranged such that the output of the preceding flip-flop is fed as an input to the immediate next flip-flop. It is to be noted that the complement output of the last flip-flop is back-fed to the first flip-flop.
Johnson’s Counter is of Synchronous type and, Number of states = 2 x Number of flip flops. Therefore, a 4-bit Johnson’s Counter can count 8 states.
- Here, the CLR signal is connected to the CLEAR input of all flip flops. Initially, CLR is low(0) and hence the counter state is 0000.
- After this, the CLR is maintained at high which will make the flip flops to produce outputs on the negative edge of incoming clock pulses based on D inputs.
The states of counter affected by each clock pulse are given below. The bit patterns repeat after every 8 clock cycles.
| CLR | Clock | |
|
|
|
|---|---|---|---|---|---|
| 0 | X | 0 | 0 | 0 | 0 |
| 1 | ???? | 1 | 0 | 0 | 0 |
| 1 | ???? | 1 | 1 | 0 | 0 |
| 1 | ???? | 1 | 1 | 1 | 0 |
| 1 | ???? | 1 | 1 | 1 | 1 |
| 1 | ???? | 0 | 1 | 1 | 1 |
| 1 | ???? | 0 | 0 | 1 | 1 |
| 1 | ???? | 0 | 0 | 0 | 1 |
| 1 | ???? | 0 | 0 | 0 | 0 |