Multiplexers | Computer Organization And Architecture Tutorials

In this page

Multiplexer(MUX) is a device that allows digital signals from several sources to be routed onto a single line of output. It has several input lines and a single output line. It has also data selector lines which specifies which input signal has to be switched to the output line. n data selector lines are required for routing 2ⁿ input lines.

4-input Multiplexer

A 4-input multiplexer has two data-selector lines a combination of which are used to select any of the four data-input lines.

Logic symbol of a 4-input MUX is shown in figure.

If a binary 0 is applied to the data-selector lines, the data on input D₀ appear on the data-output line. If a binary 1 is applied to the data-selector lines, the data on input D₁ appear on the data-output line. If a binary 2 is applied to the data-selector lines, the data on input D₂ appear on the data-output line. If a binary 3 is applied to the data-selector lines, the data on input D₀ appear on the data-output line.

This operation is given in the table.

Data Selector		Output
S₁	S₀	Y
0	0	$D_0$
0	1	$D_1$
1	0	$D_2$
1	1	$D_3$

From the table it is clear that

$Y$ is $D_0$ only if $S_1=0$ and $S_0=0$ : $Y=D_0 \overline S_1 \overline S_0.$
$Y$ is $D_0$ only if $S_1=0$ and $S_0=1$ : $Y=D_1 \overline S_1 S_0.$
$Y$ is $D_0$ only if $S_1=1$ and $S_0=0$ : $Y=D_2 S_1 \overline S_0.$
$Y$ is $D_0$ only if $S_1=1$ and $S_0=1$ : $Y=D_3 S_1 S_0.$

The total expression for the data output is

$Y=D_0 \overline S_1 \overline S_0+D_1 \overline S_1 S_0+D_2 S_1 \overline S_0+D_3 S_1 S_0$

This can be implemented using four 3-input AND gates, a 4-input OR gate, and two inverters as shown in the figure.

8-input Multiplexer

An 8-input multiplexer has three data-selector lines a combination of which is used to select any of the eight data-input lines.

Logic symbol of a 8-input MUX is shown in figure.

The operation of 8:1 MUX is described in the truth table.

Data Selector			Output
S2	S1	S0	Y
0	0	0	$D_0$
0	0	1	$D_1$
0	1	0	$D_2$
0	1	1	$D_3$
1	0	0	$D_4$
1	0	1	$D_5$
1	1	0	$D_6$
1	1	1	$D_7$

The expression for the data output can be derived from the truth table

$Y=D_0 \overline{S_2} \overline{S_1} \overline{S_0}+D_1\overline{S_2}\overline{S_1}{S_0}+D_2\overline{S_2}S_1\overline{S_0}+D_3\overline{S_2}{S_1}{S_0}+D_4S_2\overline{S_1}\overline{S_0}+D_5S_2\overline{S_1}S_0+D_6S_2S_1\overline{S_0}+D_7S_2S_1S_0$

This can be implemented using eight 4-input AND gates, an 8-input OR gate, and three inverters.

Higher-Order MUX Using Lower Order MUX

Multiplexers can also be implemented using a set of lower order multiplexers. Construction of an 8×1 multiplexer using 4×1 and 2×1 multiplexers is shown in the figure.

4-input Multiplexer

8-input Multiplexer

Higher-Order MUX Using Lower Order MUX

Further Reading