To add an N-bit number, multiple full adder circuits can be cascaded parallelly. A ripple-carry adder is created by connecting carry output of each full-adder with the carry input of the next higher-order full-adder. The input carry should occur first to produce the sum and output carry of any stage (a stage is one full adder); this causes a time delay in the addition process.
Full-adder 1 (FA1) cannot produce a potential carry until an input carry is applied. Full-adder 2(FA2) cannot produce a potential output carry until FA1 produces an output carry, Full-adder 3(FA3) cannot produce a potential output carry until FA2 produces an output carry and so on. That is the input carry has to ripple through all the adders before a final sum is produced.