JK Flip flop

The JK Flip flop can be viewed as a modification of the SR Flip flop. The intermediate state in a JK Flip flop is more refined and precise than that of an SR Flip flop.

jk flip flop block diagram

Design of JK Flip flop

The design of a JK Flip flop is similar to that of an SR Flipflop. The Q output is connected back to the input of NAND gate G_2 and \overline Q output is connected back to the input of NAND gate G_1.

jk flip flop circuit diagram
JK Flip flop circuit diagram

Working of JK Flip flop

When J is 1 and K is 0, the Q output goes 1 on the triggering edge of the clock pulse, and the flip-flop is SET. When J is 0 and K is 1, the Q output goes 0 on the triggering edge of the clock pulse, and the flip-flop is RESET.

When both J and K are 0, the output does not change from its prior state. When J and K are both 1, the output of the JK flip-flop will toggle between 1 and 0. This is called the race-around condition in a JK Flipflop. This is described in the following truth table.

ClkJKQ_{n+1}
0XXQ_n
100Q_n
1010
1101
111\overline Q_n (Toggle)

Truth table

Q_nJKQ_{n+1}
0000
0010
0101
0111
1001
1010
1101
1110

Characteristic table

Q_nQ_{n+1}JK
000X
011X
10X1
11X0

Exctitation table

Expressions for J, K and Q_{n+1} can be obtained from the table using the K-Map technique as follows.

jk flipflop kmap

Subscribe
Notify of
guest
0 Comments
Inline Feedbacks
View all comments