Asynchronous Up/ Down Counter

An up-down counter is a combination of an up-counter and a down-counter. It can count in both directions, increasing as well as decreasing.

A mode control input(M) is used to select either up or down mode.

we have the M(mode control) input which decides whether Q or \overline Q should be the clock
input to the next flip flop. We have to design a combinational circuit, that when applied M = 0 gives up counting and when M = 1 gives down counting.

up down counter combinational circuit used

The combination of inputs to the combinational circuit that we have to design and the corresponding output it should produce is given below. The equation for Y can be found out using K-Map.

MQ\overline QY
0000
0010
0101
0111
1000
1011
1100
1111
k map up down counter combinational circuit

Hence from the k-map, we got the equation in sum-of-product terms as Y = \overline M Q + M \overline Q.

A 4 bit up/ down counter can be designed as follows.

4 bit asynchronous up down counter 4

AND gates 1, 3 and 5 has one input connected with \overline M input and the other input from Q
output of flip flop preceding it. Similarly, gates 2, 4 and 6 have input from M and \overlineQ.

  • When M = 0, gates 1, 3 and 5 gives Q as output and gates 2, 4 and 6 gives 0.
  • When these outputs are given to OR gate, it produces Q as output, which is connected to the clock input of next flip flop.
  • Hence, we have up counting.
  • When M = 1, gates 1, 3 and 5 gives 0 as output and gates 2, 4 and 6 gives Q as output.
  • When these outputs are given to OR gate, it produces Q as output, which is connected to the clock input of next flip flop.
  • Hence, we have down counting.

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